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الخميس، 12 يوليو 2018

Parallel scanline algorithm for rapid rasterization of vector geographic data


Parallel scanline algorithm for rapid 

rasterization of vector geographic data

Yafei Wang, Zhenjie Chen, Liang Cheng n

, Manchun Li nn, Jiechen Wang

Jiangsu Provincial Key Laboratory of Geographic Information Science and Technology, Nanjing University, 22 Hankou Road, Nanjing 210097, China

Computers & Geosciences Volume 59, September 2013, Pages 31-40 :

 Abstract

   With the expansion of complex geographic calculations and the increase of spatial data types involved in the spatial analysis of large areas, the need becomes urgent for fast rasterization of massive multi-source geographic vector data. A parallel scanline algorithm is proposed for rapid rasterization. It provides a systematic solution to solve the complicated situation in parallel processing (cross-processor boundaries, common boundaries, and tiny polygons), thus ensuring the accuracy of the parallel scanline algorithm. The relationship of parallel speedup with the number of processors, the data partition pattern, and the raster grid size is discussed. Massive vector geographic data (approximately 0.7 million polygons) used in the experiment were effectively processed, thereby dramatically reducing the processing time and getting good speedup.

Keywords: Vector geographic data Rasterization Parallel processing Scanline Speedup


1. Introduction 

   Vector data and raster data are the two basic geographic data types used in the Geographic Information System (GIS) (Maguire et al., 1991), and the latter is more suitable for spatial analysis and spatial simulation (Goodchild, 2011). As satellite technologies advance forward, raster data have become increasingly more popular than vector data. At present, raster data is already the most dominant format used by data sources. With the expansion of complex geographic calculations and the increase of spatial data types involved in the spatial analyses on large areas (Lee et al., 2011), the need for rasterization of massive multi-sourced vector geographic data becomes more and more urgent. However, due to the sequential architecture of existing rasterization algorithms and the traditional desktop computer platform, current solutions cannot meet the strong demand of fast rasterization on massive vector geographic data. In recent years, the gradual popularity of the new parallel hardware architecture, such as computer clusters and multi-core processors, offers a new opportunity to improve the conversion speed of massive geographic data, which had been restricted by the limited computing performance of older technologies (Kenneth et al., 2003; Gong and Xie, 2009). To achieve the requirements of rapid rasterization on massive vector data, it is necessary to combine geographic data conversion technology with parallel hardware architecture by developing new parallel algorithms, thereby reducing processing time through parallel computing (Mariethoz, 2010; Schiele et al., 2012).

    Parallel rasterization of vector geographic data includes parallel rasterization of point data, of line data, and of polygon data. Among these three, parallel rasterization of polygon data is relatively complex. Therefore, this paper focuses on the study of parallel rasterization algorithms on polygon data. Based on the analysis of the limitations of the existing researches, a new parallel scanline algorithm for rapid rasterization of vector polygon data is proposed. Its main procedures include: (1) Executing particle-sized partitions on vector polygon data, according to the number of processors and the spatial location of the vector polygon data, so as to adapt to different-sized grid blocks, and (2) Fusing partition parts, in which a parallel strategy using pixel-center scanlines is proposed to solve the complicated situation, including cross-processor boundaries, common boundaries, and tiny polygons.

   The algorithm was implemented for multi-core processors. The land use data of Changsha City, China was used to check the performance of this algorithm, and the results were compared with those derived from the commercial software ArcGIS. Meanwhile, this research measures the operating time and speedup of this parallel algorithm, and this paper discusses the relationship of the parallel speedup with the number of processors, the data partition pattern, and the grid cell size.



Fig. 2. Parallel scanline processing of the cross-processor boundaries. (a) Vector Polygon A and B operated in parallel by Processors 0 and 1 (the blue and red boundaries named as cross-processor boundaries), (b) Scanline operation performed to two polygons in Processor 0 and 1, simultaneously, (c) The corresponding rasterization results (gray and pink area) to Polygon A and B (green area not involved in rasterization based on pixel center-based scanline algorithm). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)


6. Conclusion 

  This paper proposes a parallel scanline algorithm for rapid rasterization of massive geographic vector data. The following conclusions were reached based on our experimental analysis 

(a) Massive geographic vector data (about 0.7 million polygons) used in the experiment were effectively processed, dramatically reducing the data transformation time and achieving good speedup. 

(b) In comparison to the rasterization results from the ArcGIS software, the parallel algorithm leads to almost identical results, thus ensuring a high accuracy. 

(c) The speedup of this algorithm can be optimized by selecting the number of processors, the data partition pattern, and the raster grid size.

   However, the parallel efficiency of this algorithm is related to the spatial distribution of the vector polygons. A better scheduling strategy might achieve greater parallel efficiency; therefore, this requires further study and experiment. Further research is needed on finding the right balance among raster grid size, number of processors, and speedup, in order to make full use of the existing hardware architecture to meet the specific application requirements.


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